TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 743

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMACA1
HDMACB1
HDMAM1
Symbol
HDMAS1
HDMAD1
(12) DMAC (2/7)
DMA
source
address
Register1
DMA
destination
address
Register1
DMA
Transfer
count
number A
Register1
DMA
Transfer
count
number B
Register1
DMA
transfer
Mode
Register1
Name
Address
091AH
091BH
091CH
0910H
0911H
0912H
0914H
0915H
0916H
0918H
0919H
D1SA15
D1SA23
D1DA15
D1DA23
D1CA15
D0CB15
D1CA7
D1CB7
D1SA7
D1DA7
7
0
0
0
0
0
0
0
0
0
0
D1SA14
D1SA22
D1DA14
D1DA22
D1CA14
D0CB14
D1SA6
D1DA6
D1CA6
D1CB6
6
0
0
0
0
0
0
0
0
0
0
92CF26A-742
Set transfer-count-number A for DMA1 (15:8)
Set transfer-count-number B for DMA1 (15:8)
D1SA13
D1SA21
D1DA13
D1DA21
D1CA13
D0CB13
Set transfer-count-number A for DMA1 (7:0)
Set transfer-count-number B for DMA1 (7:0)
D1DA5
D1CA5
D1CB5
D1SA5
Set destination address for DMA1 (23:16)
Set destination address for DMA1 (15:8)
Set destination address for DMA1 (7:0)
5
0
0
0
Set source address for DMA1 (23:16)
0
0
0
0
0
0
0
Set source address for DMA1 (15:8)
Set source address for DMA1 (7:0)
100: Source/destination INC
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
101: Source/destination DEC
110: Source/destination fixed
111: Reserved
D1SA12
D1SA20
D1DA12
D1DA20
D1CA12
D0CB12
D1SA4
D1DA4
D1CA4
D1CB4
D1M4
(MEM → MEM)
4
0
0
0
0
0
0
0
0
0
0
0
(MEM → MEM)
(I/O→ I/O)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D1SA11
D1SA19
D1DA11
D1DA19
D1CA11
D0CB11
D1SA3
D1DA3
D1CA3
D1CB3
D1M3
3
0
0
0
0
0
0
0
0
0
0
0
D1SA10
D1SA18
D1DA10
D1DA18
D1CA10
D0CB10
D1SA2
D1DA2
D1CA2
D1CB2
D1M2
R/W
2
0
0
0
0
0
0
0
0
0
0
0
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
D1DA17
D1SA17
D1SA9
D1DA1
D1DA9
D1CA1
D1CA9
D1CB1
D0CB9
D1SA1
D1M1
1
0
0
0
0
0
0
0
0
0
0
0
TMP92CF26A
2007-11-21
D1SA16
D1DA16
D1SA0
D1SA8
D1DA0
D1DA8
D1CA0
D1CA8
D1CB0
D0CB8
D1M0
0
0
0
0
0
0
0
0
0
0
0
0