TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 599
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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A Read-
modify- write
operation
cannot be
performed
PAGER
(1327H)
RESTR
(1328H)
A Read-
modify-
write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note: Please keep the setting order below of <ENATMR>, <ENAAML> and <INTENA>. Set difference time for
Example: Clock setting/Alarm setting
(10) PAGE register (for PAGE0/1)
(11) Reset register (for PAGE0/1)
Clock/Alarm setting and interrupt setting.
1Hz
0: Enable
1: Disable
DIS1HZ
Interrupt
0: Disable
1: Enable
RSTTMR
RSTALM
ld
ld
INTENA
<DIS1HZ>
7
R/W
7
0
1
0
1
(pager), 0ch
(pager), 8ch
16Hz
0: Enable
1: Disable
DIS16HZ
6
6
0
1
0
1
“0” is read.
<DIS16HZ>
1:Clock
Others
RSTTMR
reset
1
1
0
Unused
Reset alarm register
Unused
Reset clock register
92CF26A-598
:
:
5
5
ADJUST
Clock, Alarm enable
Interrupt enable
PAGE
1:Alarm
0: Don’t
1: Adjust
PAGER<ENAALM>
RSTALM
Undefined
reset
ADJUST
4
W
4
care
Undefined
1
0
0
W
0
1
0
1
Clock
0: Disable
1: Enable
ENATMR
3
−
3
Select Page0
Select Page1
Don’t care
Adjust sec. counter.
When this bit is set to “1” the sec. counter
becomes to “0” when the value of the sec.
counter is 0-29. When the value of the sec.
counter is 30-59, the min. counter is carried and
sec. counter becomes "0". Output Adjust signal
during 1 cycle of f
once, Adjust is released automatically.
(PAGE0 only)
Undefined
Interrupt source signal
R/W
ALARM
0: Disable
1: Enable
ENAALM
Output “0”
Always write “0”
2
−
Alarm
16Hz
2
1Hz
SYS
. After being adjusted
“0” is read.
1
−
1
TMP92CF26A
2007-11-21
PAGE
selection
Undefined
PAGE
R/W
0
−
0
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