TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 255

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

NDFDTR1
(1FF2H)
(1FF3H)
NDFDTR0
(1FF0H)
(1FF1H)
Note: Although these registers allow both read and write operations, no flip-flop is incorporated. Since write and read
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
accessing the NDFDTR0 register. When you write to this register, the data is written to the
NAND Flash. When you read from this register, the data is read from the NAND Flash.
The NDFDTR0 register is used for both channel 0 and channel 1.
example, 4 bytes of data can be transferred from 32-bit internal RAM to 8-bit NAND Flash
memory by DMA operation by setting the destination address as NDFDTR0. (NDFDTR1
cannot be set as the destination address.) The actual DMA operation is performed by first
reading 4 bytes from the internal RAM and then writing 1 byte to the NAND Flash four
times from the lowest address.
details, see Table3.11.3.
Write and read operations to and from the NAND Flash memory are performed by
A total of 4 bytes are provided as data registers to enable 4-byte DMA transfer. For
To access data in the NAND Flash, be sure to access NDFDTR0 (at address 1FF0). For
operations are performed in different manners, it is not possible to read out the data that has been just written.
Figure3.11.6 NAND Flash Data Registers (NDFDTR0, NDFDTR1)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
D15
D15
15
15
D7
D7
7
7
D14
D14
D6
14
D6
14
6
6
NAND Flash Data Register 0
NAND Flash Data Register 1
92CF26A-254
D13
D13
13
13
D5
D5
5
5
NAND Flash Data Register (15-8)
NAND Flash Data Register (15-8)
NAND Flash Data Register (7-0)
NAND Flash Data Register (7-0)
D12
D12
D4
12
D4
12
4
4
R/W
R/W
R/W
R/W
D11
D11
D3
11
D3
11
3
3
D10
D10
10
10
D2
D2
2
2
D9
D1
D9
D1
9
1
9
1
TMP92CF26A
2007-11-21
Undefined
Undefined
D0
D8
D0
D8
0
8
0
8