TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 633

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

A read-
modify-write
operation
cannot be
performed
WDMOD
(1300H)
WDCR
(1301H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
WDT control
1: Enable
WDTE
7
7
1
Figure 3.24.5 Watchdog Timer Control Register
Figure 3.24.4 Watchdog Timer Mode Register
Select detecting time
00: 2
01: 2
10: 2
11: 2
WDTP1
R/W
6
15
17
19
21
6
0
/f
/f
/f
/f
IO
IO
IO
IO
WDTP0
92CF26A-632
5
5
0
B1H: WDT disable code
4EH: WDT clear code
4
4
W
Watchdog timer out control
IDLE2 control
Watchdog timer detection time
Watchdog timer enable/disable control
−
−
00
01
10
11
0
1
0
1
0
1
Others
B1H
4EH
−
Connects WDT out to a reset
Stop
Operation
Disabled
Enabled
3
2
2
2
2
3
15
17
19
21
WDT disable/clear control
/f
/f
/f
/f
IO
IO
IO
IO
(Approximately 819.2 μs at f
(Approximately 3.276 ms at f
(Approximately 13.107 ms at f
(Approximately 52.428 ms at f
Disable code
Clear code
Don’t care
IDLE2
0: Stop
1: Operate
I2WDT
2
2
0
1: Internally
connects
WDT out to
the reset
pin
RESCR
R/W
1
1
0
TMP92CF26A
2007-11-21
IO
IO
Always
write “0”
IO
IO
= 40 MHz)
= 40 MHz)
= 40 MHz)
= 40 MHz)
0
0
−
0