TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 75

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Symbol
DMAR
DMA
Request
Name
(2) Soft start function
(3) Transfer control registers
Note1: If it is started by software, don’t set any channels to start in same time.
Note2: If be started sequentially, restart it after confirming micro DMA of all channels is completed (all micro DMA are
using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is
initiated by a Write cycle which writes to the register DMAR.
performed once. On completion of the transfer, the bits of DMAR for the completed
channel are automatically cleared to “0”.
transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) become “0”.
from the initiation of micro DMA until the value in the micro DMA transfer counter is
“0”.
following registers. An instruction of the form LDC cr,r can be used to set these
registers.
set to “0”).
Address
The TMP92CF26A can initiate micro DMA/HDMA either with an interrupt or by
Writing “1” to each bit of DMAR register causes micro DMA or HDMA to be
When writing again “1” to it, soft start can execute continuously until the DMA
When a burst is specified by the register DMAB, data is transferred continuously
The transfer source address and the transfer destination address are set in the
(Prohibit
RMW)
109H
Channel 0
Channel 7
DMAS0
DMAD0
DMAS7
DMAD7
32 bits
DREQ7
DMAC0
DMAC7
7
0
16 bits
DMAM0
DMAM7
8 bits
DREQ6
6
0
92CF26A-74
Micro DMA source address register 0
Micro DMA destination address register 0
Micro DMA counter register 0
Micro DMA source address register 7
Micro DMA destination address register 7
Micro DMA counter register 7
Micro DMA mode register 0
Micro DMA mode register 7
DREQ5
5
0
DREQ4
4
0
1: Start DMA
R/W
DREQ3
3
0
DREQ2
2
0
DREQ1
TMP92CF26A
1
0
2007-11-21
DREQ0
0
0