TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 342

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Protocol
1.
2.
3.
4.
5.
6.
Select 9-Bit UART Mode on the master and slave controllers.
Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
The master controller transmits data one frame at a time. Each frame includes an 8-bit
select code which identifies a slave controller. The MSB (bit 8) of the data (<TB8>) is
set to 1.
Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its <WU>
bit to 0.
The master controller transmits data to the specified slave controller (the controller
whose SC0MOD0<WU> bit has been cleared to 0). The MSB (bit 8) of the data
(<TB8>) is cleared to 0.
because their MSBs (bit 8 or <RB8>) are set to 0, disabling INTRX0 interrupts.
The slave controller whose <WU> bit = 0 can also transmit to the master controller. In
this way it can signal the master controller that the data transmission from the
master controller has been completed.
The other slave controllers (whose <WU> bits remain at 1) ignore the received data
Start
Start
Bit0
Bit0
1
1
Select code of slave controller
2
2
92CF26A-341
3
3
Data
4
4
5
5
6
6
7
7
“1”
Bit8
8
“0”
Stop
Stop
TMP92CF26A
2007-11-21