TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 497

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SPIST
(824H)
(825H)
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
(3-1) SPI Status Register (SPIST)
(a) TEMP
(b) TEND
(c) REND
The SPIST register contains three bits that indicates the status of data communication.
(SPITD) contains valid data; otherwise, it is set to 1.
buffer contains no valid data.
transmit data, and also when the transmission is in progress. This bit is set to 1 after
completing the data transmission where the SPITD register and the transmit FIFO
contain no valid data.
valid data is stored into the receive data register (if there is any valid data). This bit is
cleared to 0 when the receive register (SPIRD) contains no valid data, or when the
reception is in progress.
full with the valid data after completing the reception of the last data. This bit is
cleared to 0 when there is still an empty space of one byte or more in the FIFO.
flag.
For UNIT-mode transmission, this bit is cleared to 0 when the transmit register
For Sequential-mode transmission, this bit is set to 1 when the transmit FIFO
This bit is cleared to 0 when the SPITD register or the transmit FIFO contains valid
For UNIT-mode reception, this bit is set to 1 when completing the data reception and
For Sequential-mode reception, this bit is set to 1 when the 32-byte receive FIFO is
The RFUL flag does not exist because its function is exactly the same as the REND
15
7
14
6
Figure 3.17.9 SPIST Register
13
5
SPIST Register
92CF26A-496
12
4
Transmit
FIFO
Status
0: No empty
space
1: Hasan
empty space
TEMP
11
3
R
1
10
2
Transmission
Status
0:
Transmission
in progress
or having
transmit data
1:
Transmission
ended
TEND
1
1
9
R
Reception
Status
0: Reception
in progress
or not having
receive data
1: Reception
Ended or
FIFO full
TMP92CF26A
REND
0
8
2007-11-21
0