TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 240

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.10.3
as the transfer source.
•
The following shows an example of calculating the HDMA transfer time when SDRAM is used
An Example of Calculating HDMA Transfer Time
Transfer from SDRAM to internal SRAM
Conditions:
System clock (f
SDRAM read cycle
16-bit data bus
SDRAM Auto Refresh interval: 936 states (15.6 μs)
Internal RAM write cycle
Number of bytes to transfer
Calculation example:
(a) Read/write time
(b) Burst start/stop time
(c) Auto Refresh time
Transfer time = (SDRAM read time + SRAM write time) × transfer count
Total transfer time = (a) + (b) + (c)
is assumed that Auto Refresh occurs once here.
(SDRAM read 1 state × 2 + Internal RAM write 1 state) × 512 bytes/4 bytes
= 384 states × 1/60 MHz
= 6.4 μs
Start (TRCD: 2CLK) 5 states + Stop 2 states
= 7states/60 MHz
= 0.117 μs
Based on the above (a), Auto Refresh occurs once or zero times in 384 states. It
= 7 states × 1/60 MHz
= 0.117 μs
(Precharge (TRP: 2CLK) 2 states + AREF (TRC: 5CLK) 5 states) ×AREF once
SYS
)
+ (Precharge time + Auto Refresh time) × Auto Refresh count
+ (SDRAM burst start + stop time)
= 6.4 μs + 0.117 μs + 0.117 μs
= 6.634 μs
92CF26A-239
: 60 MHz
: Full page (5-1-1-1), 16-bit data bus
: 1 state, 32-bit data bus
: 512 bytes
TMP92CF26A
2007-11-21