TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 226

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SDCMM
(0253H)
SDBLS
(0254H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note 1: <SCMM2:0> is automatically cleared to “000” after the specified command is issued. Before writing the next
Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed.
command, make sure that <SCMM2:0> is “000”. In the case of the Self Refresh Entry command, however,
<SCMM2:0> is not cleared to “000” by execution of this command. Thus, this register can be used as a flag for
checking whether or not Self Refresh is being performed.
7
7
SDRAM HDMA Burst Length Select Register
6
6
Figure 3.10.1 Control Registers
SDRAM Command Register
For
HDMA5
SDBL5
5
5
0
92CF26A-225
For
HDMA4
SDBL4
4
4
0
1: Full page read / Burst write
0: 1 Word read / Single write
For
HDMA3
SDBLS
HDMA burst length
3
3
0
R/W
Command issue (Note 1) (Note 2)
000: Don’t care
001: Initialization sequence
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
For
HDMA2
SCMM2
SDBL2
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
2
2
0
0
For
HDMA1
SCMM1
SDBL1
R/W
1
1
0
0
TMP92CF26A
For
HDMA0
2007-11-21
SCMM0
SDBL0
0
0
0
0