TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 541

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDHSP
(028AH)
(028BH)
(Delay control)
(2) LHSYNC Signal
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
display. The LHSYNC period is defined as an integral multiple of the reference clock signal
LCP0.
the LCP0 clock period. The value to be set in LCDHSP<LH15:0> should be “segment size +
number of dummy clocks” or larger for TFT. In the case of STN, the minimum value of
LCDHSP<LH15:0> is:
also possible to set the delay time for the LVSYNC signal in units of LCP0 pulses.
The period of the horizontal synchronization signal LHSYNC corresponds to one line of
The LHSYNC period is defined as the product of the value set in LCDHSP<LH15:0> and
Monochrome/grayscale
Color
LHSYNC [s: period] = LCP0 [s: period] × (<LH15:0> + 1)
The enable width of the LHSYNC signal can be specified by LCDHSW<HSW9:0>. It is
(Enable width control)
LH15
LH7
7
0
7
0
LH14
LH6
6
6
0
0
LCD LHSYNC Pulse Register
(Phase control)
92CF26A-540
LH13
: (Segment size / 8) + number of dummy clocks
: (Segment size × 3 / 8) + number of dummy clocks
LH5
5
5
0
0
LHSYNC signal
LHSYNC period (bits 7–0)
LHSYNC period (bits 15-8)
LH12
LH4
4
0
4
0
W
W
LH11
LH3
3
3
0
0
LH10
LH2
2
2
0
0
LH1
LH9
1
0
1
0
TMP92CF26A
2007-11-21
LH0
LH8
0
0
0
0