TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 338

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SCLK0 output
(<SCLKS> = 1:
falling edge mode)
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
RXD0
IRX0C
(INTRX0 interrupt
request)
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
RXD1
IRX0C
(INTRX0 interrupt request)
Note: The system must be put in the receive-enable state (SC0MOD0<RXE> = 1) before data can be received.
b.
Figure 3.14.15 Receiving operation in I/O Interface Mode (SCLK0 Output Mode)
Figure 3.14.16 Receiving Operation in I/O interface Mode (SCLK0 Input Mode)
Receiving
data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received,
the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown
below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt to be
generated.
Setting SC0MOD0<RXE> to 1 initiates SCLK0 output.
goes active. The SCLK input goes active when the Receive Interrupt flag INTES0
<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data
is shifted to Receiving Buffer 2 (SC0BUF) following the timing shown below and
INTES0 <IRX0C> is set to 1 again, causing an INTRX0 interrupt to be generated.
In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the
In SCLK Input Mode the data is shifted to Receiving Buffer 1 when the SCLK input
Bit
92CF26A-337
Bit0
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP92CF26A
2007-11-21