TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 234

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Internal system clock
Internal data bus
COMMAND
(5) Read/Write commands
D15-D0
SDCLK
A15-A0
using SDACR<SPRE>.
Precharge. When Auto Precharge is enabled, the SDRAM is automatically precharged
internally at every access cycle. Thus, the SDRAM is always in a “bank idle” state while it is
not being accessed. This helps reduce the power consumption of the SDRAM but at the cost of
degradation in performance as the Bank Active command is needed at every access cycle.
Precharge. In this case, the SDRAM is not precharged at every access cycle and is always in a
“bank active” state. This increases the power consumption of the SDRAM, but improves
performance as there is no need to issue the Bank Active command at every access cycle. If an
access is made to outside the SDRAM page boundaries or if the Auto Refresh command is
issued, the SDRAMC automatically issues the Precharge All command.
there is one limitation. When SDRAM is set as VRAM for LCD controller and DMA controller
is operated at the same time, always set to “1” to SDACR<SPRE>.
The Read/Write commands to be used in 1-word read/single write mode can be specified by
When SDACR<SPRE> is set to “1”, the Read/Write commands are executed with Auto
When SDACR<SPRE> is set to “0”, the Read/Write commands are executed without Auto
And this micro has LCD controller and DMA controller, in case of using below condition,
(c) Full-page read, the read data shift function enabled (SDACR<SRDS> = “1”,
<SRDSCK> = “0”)
NOP
Row Address
ACTIVE
READ
92CF26A-233
External data latch
NOP
ColumnAddress
NOP
DIN1
DIN1
CPU data read
NOP
DIN2
DIN2
NOP
TMP92CF26A
DIN3
2007-11-21
DIN3