TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 583

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TMP92CF26AXBG

Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMP92CF26AXBG

Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
 Details

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3.20.3
P96/INT4 pin
touched onto the touch screen and until the pen-touch is detected.
an X/Y position measuring procedure is terminated, return to this procedure to wait for the
next touch.
three switches (SMY, SPX, SMX) to OFF. At this time, the pull-down resistor built in the
P96/INT4/PX pin is set ON..
connected, the P96/INT4/PX pin is set to Low by the internal pull-down resistor (PXD),
generating no INT4 interrupt
screen are connected, which sets the P96/INT4/PX pin to High and generates an INT4
interrupt
as shown below is provided. Setting debounce time in the TSICR1 register ignores pulses
whose time equals to or is below the set time.
and then captures the signal into the inside after counting. When the signal turns to “L”
during counting, the counter is cleared, starting to wait for a rising edge again.
Touch detection procedure
The touch detection procedure includes the procedure starting from when the pen is
Touching the screen generates the interrupt (INT4) and terminates this procedure. After
When waiting for a touch with no contact, set only the SPY switch to ON and set all other
In this state, because the internal X- and Y-direction resistors in the touch screen are not
When a next pen-touch is given, the X- and Y-direction internal resistors in the touch
To avoid generating more than one INT4 interrupt by one pen-touch, the debounce circuit
The debounce circuit detects a rising of signal to count up a set debounce counter time
Figure 3.20.3 Block diagram of debounce circuit
Debounce circuit
TSICR1
92CF26A-582
TSICR0<TWIEN>, IIMC<I4EDGE>,
And select the Rising
or Falling of INT4
F/F
Enables INT4,
TMP92CF26A
2007-11-21
TSICR0
<PTST>
INT4

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