TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 408

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

USB STATE
(07CEH)
INT_Control
(07D6H)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.16.3.22 INT_Control Register
3.16.3.23 USB STATE Register
register.
becomes disabled.
(smaller than the data length that is specified by the host as wLength), the device side
and stage management cannot be synchronized. Therefore, INT_STASN interrupt
signals this shift to status stage.
asserted at every status stage.
these bits (Configured, Addressed and Default). If transaction for SET_CONFIG
request is executed by using software, write the present state to this register. If host
appointconfig is 0, this becomes Unconfigured, and it is necessary to return to
Addressed state. Therefore, if host appoint config is 0, write “0” to bit2.
by hardware. When host appoint config value that supported by device, device must
execute mode setting for each endpoint by using the value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to “1” before accessing EOP register. When this bit is set to “1”, Addressed bit
(Bit1) is set to “0” automatically.
INT_STASN interrupt is disabled and enabled by the value that is written to this
This is initialized to disable by external reset. When setup packet is received, it
In control read transfer, if the host terminates a dataphase with small data length
If this interrupt is not required, it can set to disable because this interrupt is
This register shows the current device state for connection with USB host.
Inside the UDC, the answer for each Device Request is managed by referring to
When Configured bit (Bit2) is written “0”, Addressed bit (bit 1) is set automatically
STATUS_NAK (Bit0)
Bit2 to bit0
7
7
0: INT_STATSN interrupt disable
1: INT_STATSN interrupt enable
000: Default
010: Addressed
100: Configured
6
6
92CF26A-407
5
5
4
4
3
3
Configured
R/W
2
2
0
Addressed
1
1
R
0
TMP92CF26A
2007-11-21
Status_nak
Default
R/W
R
0
0
0
1