TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 536
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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LCDVSP
(028CH)
(028DH)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
TFT
STN
of the value set in LCDVSP<LV9:0> and the LHSYNC period.
Common size + number of dummy clocks
Common size + number of dummy clocks
(A minimum of one dummy clock must be inserted in the back porch.)
LVSYNC [s: period]
The period of the vertical synchronization signal LVSYNC is defined as the product
The value to be set in LCDVSP<LV9:0> is obtained as follows:
LVP7
7
7
0
LVP6
6
6
0
LCD LVSYNC Pulse Register
92CF26A-535
LVP5
= LHSYNC [s: period] × (<LV9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LV9:0> + 1)
5
5
0
LVSYNC period (bits 7-0)
LVP4
4
4
0
W
(*)
(*)
LVP3
3
3
0
LVP2
2
2
0
LVP1
LVP9
LVSYNC period
1
1
0
0
(bits 9-8)
TMP92CF26A
W
2007-11-21
LVP0
LVP8
0
0
0
0
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