TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 496

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

which are the transmit interrupt (INTSPITX) and receive interrupt (INTSPIRX) requests.
Also, the SPIC has four types of interrupts; two for transmission and two for reception.
the transmission mode, which is UNIT or Sequential.
performed in 16–byte units. Otherwise, the TEMP interrupt is not properly generated.
(3) Interrupts
(a) Transmit interrupts
(b) Receive interrupts
The SPIC generates two types of interrupt requests to the Interrupt Controller (INTC),
TEMP (Transmit FIFO Empty interrupt) and TEND (Transmit End interrupt)
As for the TEMP interrupt, the timing of the interrupt generation differs depending on
In the Sequencial-mode transmission, the data writes to the transmit FIFO must be
when the data written in the transmit data register (SPITD) is loaded into the
transmit shift register.
completed with the FIFO being empty (i.e., after the falling edge of the last bit clock
where SPIMD<TCPOL> = 0).
empty space size of the transmit FIFO reaches 16 bytes, and the other is when it
reaches 32 bytes.
completed with the FIFO being empty (i.e., after the falling edge of the last bit clock
where SPIMD<TCPOL> = 0).
on the reception mode; which is UNIT or Sequential.
performed in 16-byte units. Otherwise, the RFUL interrupt is not properly generated.
the same timing as the REND interrupt is generated.
receive shift register into the receive data register (SPIRD).
size of data stored into the receive FIFO reaches 16 bytes, and the other is when it
reaches 32 bytes.
UNIT–mode transmission
Since the transmit FIFO is disabled in this mode, the TEMP interrupt is generated
The TEND interrupt is generated when the transmission of the last UNIT data is
Sequential–mode transmission
The TEMP interrupt is generated by the following two conditions: One is when the
The TEND interrupt is generated when the transmission of the last UNIT data is
RFUL (Receive FIFO interrupt) and REND (Receive End interrupt).
As for the RFUL interrupt, the timing of the interrupt generation differs depending
In the Sequencial-mode transmission, the data reads from the receive FIFO must be
UNIT-mode reception
Since the receive FIFO is disabled in this mode, the RFUL interrupt is generated at
The RFUL and REND interrupts are generated when the data is loaded from the
Sequential-mode reception
The RFUL interrupt is generated by the following two conditions: One is when the
The REND interrupt is generated when the 32-byte receive FIFO becomes full.
92CF26A-495
TMP92CF26A
2007-11-21