TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 553

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDDVM1
(0284H)
LCDCTL0
(0285H)
LCDDVM0
(0283H)
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
PIP
function
0:Disable
1:Enable
FMP3
FMP7
PIPE
7
7
0
0
7
0
Segment
data
0: Normal
1: Always
output “0”
LCP0 DVM (bits 3-0)
LCP0 DVM (bits 7-4)
FMP2
FMP6
6
6
R/W
0
0
ALL0
0
6
LCD Control 0 Register
Divide FRM 0 Register
Divide FRM 1 Register
92CF26A-552
Frame
divide
setting
0: Disable
1: Enable
FMP1
FMP5
FRMON
5
5
0
0
0
5
Always
write “0”
FMP0
FMP4
4
4
0
0
R/W
4
0
−
R/W
R/W
FML3
FML7
3
3
0
0
3
LHSYNC DVM (bits 3-0)
LHSYNC DVM (bit 7-4)
FR signal
LCP0/Line
selection
0:Line
1:LCP0
FML2
FML6
2
2
0
0
DLS
2
0
LCP0(Note
0: Always
1: At valid
LLOAD
0: At setting
1: At valid
FML1
FML5
width
LCP0OC
output
data only
in register
data only
1
1
0
0
R/W
1
0
TMP92CF26A
2007-11-21
FML0
FML4
LCDC
operation
0: Stop
1: Start
START
0
0
0
0
0
0