TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 31

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Limitations on the use of PLL0
X: Don't care
X: Don't care
X: Don't care
X: Don't care
X: Don't care
X: Don't care
LUP:
1. When stopping PLL operation during PLL0 use, execute the following settings in the
2. When shifting to STOP mode during PLL use, execute the following settings in the same
(1) Start Up / Change Control
(2) Change / Stop Control
(OK) High frequency oscillator operation mode(f
(OK) PLL0 use mode (f
(OK) PLL0 use mode (f
(NG) PLL0 use mode (f
Examples of settings are shown below:
same order.
order.
→ PLL0 use mode (f
→ PLL0 Stop
→High frequency oscillator operation mode (f
→ HALT(High frequency oscillator stop)
→ HALT(High frequency oscillator stop)
LD
LD
LD
LD
LD
HALT
LD
BIT
JR
LD
LD
LD
LD
LD
LD
HALT
LD
HALT
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
(SYSCR2), XXXX01XXB
(PLLCR0), X0XXXXXXB
(PLLCR1), 0XXXXXXXB
(PLLCR1), 1XXXXXXXB
5,(PLLCR0)
Z,LUP
(PLLCR0), X1XXXXXXB
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
(SYSCR2),XXXX01XXB
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
(SYSCR2),XXXX01XXB
PLL
PLL
PLL
PLL
) → Set the STOP mode
)→ High frequency oscillator operation mode(f
) → Set the STOP mode
)
92CF26A-30
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Set the STOP mode
Change the system clock f
Stop PLL0
Shift to STOP mode
PLL0 start up / lock up start
Check for lock up end flag
Change the system clock f
Change the system clock f
Stop PLL0
Set the STOP mode
(This command can be executed before use of PLL0)
Change the system clock f
Stop PLL0
Shift to STOP mode
Set the STOP mode
(This command can be executed before use of PLL0)
Shift to STOP mode
Change the clock f
Stop PLL0
OSCH
OSCH
)→PLL0 start up
) → PLL stop
PLL
to f
OSCH
PLL
OSCH
PLL
PLL
to f
to f
to f
to f
OSCH
OSCH
OSCH
PLL
TMP92CF26A
OSCH
2007-11-21
)