TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 530

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Signal Name
LCP0 signal
(Only at valid data output)
(Always output)
LFR signal (FREDGE=0)
(Frame divide control)
(Line)
(Dot)
LLOAD signal
LD23-LD0 signal
LDINV signal
LLOAD signal details
LFR signal (FREDGE=1)
LVSYNC signal
(Enable width control)
(Phase control)
DLS=0 (Line inversion)
LHSYNC signal
LLOAD signal
LGOEn signal
(Enable width control)
(Phase control)
(Delay control)
3.19.3.4 Basic Operation
LCDC and adjustable elements. The adjustable elements for each signal include
enable time, phase, and delay time.
(STN/TFT) and specifications to be used.
The following diagram shows the basic timings of the waveforms generated by the
The signals used and their connections and settings vary with the LCD driver type
(Enable width control)
(Enable width control)
(Delay control)
(Line divide)
(Line divide)
(Phase control)
(Valid data output)
92CF26A-529
(Phase control)
(Phase control)
Frame period (Refresh rate)
(Dot divide)
(Dot divide)
TMP92CF26A
2007-11-21