TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 28
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
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3.3.3
0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
reduces power consumption.
is necessary for the warming up time to elapse before the change occurs after writing the
register value.
is executed by the clock gear before changing. To execute the instruction following the clock
gear switching instruction by the clock gear after changing, input the dummy instruction
as follows (instruction to execute the write cycle).
internal I/O.
SYSCR1<GEAR2:0> sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8, fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
be PLL-OFF mode and cause the system clock (f
X2 pins.
System clock controller
(1) Clock gear controller
SYSCR1
(Example)
SYSCR1
f
(Example)
Changing clock gear
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It
There is the possibility that the instruction following the clock gear changing instruction
The system clock controller generates the system clock signal (f
SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator.
The combination of settings <XEN> = “1”, <SYSCK> = “0” and <GEAR2 to 0> = “100” will
For example, f
SYS
X: don't care
is set according to the contents of the Clock Gear Select Register SYSCR1<GEAR2:
EQU
LD
LD
EQU
LD
LD
Instruction to be executed after clock gear changed
SYS
10E1H
(SYSCR1),XXXXX001B
(DUMMY),00H
10E1H
(SYSCR1),XXXXX010B
(DUMMY),00H
is set to 625 kHz when the 10MHz oscillator is connected to the X1 and
92CF26A-27
;
;
;
Changes system clock f
Dummy instruction
Changes f
Dummy instruction
SYS
SYS
) to be set to fc/16 after reset.
to fc/4
SYS
to fc/2
SYS
) for the CPU core and
TMP92CF26A
2007-11-21
SYS
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