TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 94

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMACBn
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
(4) HDMACBn (DMA Transfer Count B Setting Register)
made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one
request, FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count
B is updated by DMA execution, HDMACBn is also updated.
The HDMACBn register is used to set the number of times a DMA request is to be
HDMACB0 to HDMACB5 have the same configuration.
DnCB15
DnCB7
Transfer count B
15
7
0
0
(090BH)
(091BH)
(092BH)
(093BH)
(094BH)
(095BH)
[15:8]
DnCB14
DnCB6
14
6
0
0
Figure3.6.5 HDMACBn Register
DnCB13
DnCB5
HDMACBn Register
13
5
0
0
Transfer count B
92CF26A-93
Transfer count B [15:8] for DMAn
Transfer count B [7:0] for DMAn
HDMACB0
HDMACB1
HDMACB2
HDMACB3
HDMACB4
HDMACB5
(090AH)
(091AH)
(092AH)
(093AH)
(094AH)
(095AH)
[7:0]
DnCB12
DnCB4
12
4
0
0
R/W
R/W
DnCB11
DnCB3
11
3
0
0
DnCB10
DnCB2
10
2
0
0
DnCB1
DnCB9
1
9
0
0
TMP92CF26A
DnCB0
DnCB8
2007-11-21
0
8
0
0