TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 552
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
- Current page: 552 of 767
- Download datasheet (6Mb)
LHSYNC (Expansion)
LVSYNC
LHSYNC
LCP0
LFR
<FREDGE>=0
<FRMON> = 1
<FMP7:0> = N
<FML7:0> = M
<DLS> = 1
Note: prohibit to set <FREDGE>=1, always need to set <FREDGE>=0.
intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of “LCP0
× M”. The “M” value is specified in LCDDVM0<FMP7:4>.
When LCDCTL0<FRMON>= “1” and LCDCTL0<DLS>= “1”, frame output is inverted at
When <DLS>= “1” LFR signal synchronous with front edge of LHSYNC signal.
So, prohibit to set <FREDGE>= “1”, always need to set <FREDGE>= “0”.
N
M
M
92CF26A-551
TMP92CF26A
2007-11-21
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