TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 444

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(d-2) Isochronous receiving mode
•
•
by OUT token is received to the CPU in the next frame.
condition or Y condition. The flow below explains X Condition (packet A) and Y
Condition (packet B) in present frame.
X. FIFO for storing data received from host in present frame
Y. FIFO for storing data for transmitting host in previous frame
Transaction format for Isochronous transfer type in receiving is given below.
Control flow
Isochronous transfer type is frame management. And data that is written to FIFO
Below are two conditions in FIFO of Isochronous receiving mode transferring
FIFO that is divided into two (packet A and packet B) conditions is whether X
X and Y conditions change one after the other by receiving SOF.
Below is control flow in the UDC when receiving OUT token.
The whole transaction is processed by hardware.
The UDC finishes normally by the above transaction.
The CPU takes back packet A’s data.
1. Token packet is received and address endpoint number error is confirmed, and it
2. Condition of status register is confirmed.
3. Data packet is received.
4. After last data has been transferred, and counted CRC is compared with
5. The transaction when SOF token from host is received is given below.
Token
Data
(DATASET register bit = 0)
(DATASET register bit = 1)
• INVALID condition: State return to IDLE.
Data is transferred from SIE into the UDC to packet A’s FIFO (X Condition).
• Change packet A’s FIFO from X Condition to Y Condition.
• Change packet B from Y Condition to X Condition, and clear data. Prepare
• Set frame number to frame register.
• Assert SOF and inform externally that frame is incremented.
• DATASET register set packet A bit and clear packet B bit arrangement
• If CRC comparison result agrees it, DATAIN is set to STATUS. If result does
checks whether the relevant endpoint transfer mode corresponds with the
OUT token. If it does not correspond, the state returns to IDLE.
transferred CRC. When transfer is finished, the result is reflected to STATUS.
However, data is stored FIFO, data number that packet A is received is set to
DATASIZE register of packet A.
for next transfer.
loading in present frame.
not agree, RX_ERR is set to STATUS.
:OUT
: DATA0
92CF26A-443
TMP92CF26A
2007-11-21