TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 368
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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(4) Stop condition generation
writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the
contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been generated
on the bus. When the bus’s SCL line has been pulled Low by another device, the
TMP92CF26A generates a stop condition when the other device has released the SCL
line and SDA pin rising.
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Internal SCL
SCL Pin
SDA Pin
<PIN>
<BB> (Read)
SBICR2 ← 1 1 0 1 1 0 0 0
When SBISR<BB> = “1”, the sequence for generating a stop condition start by
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Internal SCL
SCL pin
SDA Pin
<PIN>
<BB> (Read)
Figure 3.15.18 Stop condition generation (Single master)
Figure 3.15.19 Stop condition generation (Multi master)
7 6 5 4 3 2 1 0
92CF26A-367
The case of pulled low
by another device
Generate stop condition.
Stop condition
Stop condition
TMP92CF26A
2007-11-21
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