TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 89

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.6
DMAC (DMA Controller)
can realize data transfer faster than the micro DMA function by the 900/H1 CPU.
The TMP92CF26A incorporates a DMA controller (DMAC) having six channels. This DMAC
The DMAC has the following features:
3) Various source/destination combinations
4) Transfer address mode
5) Dual-count mechanism and DMA end interrupt
6) Priorities among DMA channels (the same as the micro DMA acceptance specifications
7) DMAC bus occupancy limiting function
8) The DMAC can be used in HALT (IDLE2) mode.
1) Six independent channels of DMA
2) Two types of transfer start requests
of the INTC)
request can be selected for each channel.
from the following four types: memory to memory, memory to I/O, I/O to memory, I/O to
I/O.
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine
can be used to prepare for the next processing.
than one request is asserted simultaneously or it looks as if two requests were asserted
simultaneously because one of the requests has been put on hold while other processing
was being performed, the smaller-numbered channel is given a higher priority.
excessive interference with the CPU or LCDC operation.
Hardware request (using an interrupt source connected with the INTC) or software
The combination of transfer source and destination can be selected for each channel
Only the dual address mode is supported.
Two count registers are provided to execute multiple DMA transfers by one DMA
DMA requests are basically accepted in the order in which they are asserted. If more
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
92CF26A-88
TMP92CF26A
2007-11-21