TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 490

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(j) RXMOD
system operation.
the data transmission is completed.
reception, it is prohibited to change the reception mode from Sequential to UNIT, or
vice versa.
interrupt is generated when the received data is loaded from the receive shift register
to the receive data register (SPIRD).
interrupt is generated when the size of received data stored in the receive FIFO
reaches 16 or 32 bytes.
Important Note:
When the SPICT<TEX> bit is set to 1, the state of any bits must not be changed until
For UNIT-mode reception, the receive FIFO buffer is disabled and the RFUL
For sequential-mode reception, the 32-byte receive FIFO is enabled and the RFUL
When in UNIT mode (TXMOD = 0), the following restriction is imposed on the
This bit selects the data reception mode from UNIT and Sequential modes. During
Sample Program 1:
Wait:
Sample Program 2 (Recommend):
LD
DI
SET 3,
BIT 1,
JPZ,
RES 3,
EI
Check the transmission end flag. (SPIST<TEND> = 1)
LD
DI
SET 3,
RES 3,
EI
(SPITDx), A
(SPICT)
(SPICT)
(SPITDx), A
(SPICT)
(SPIST)
Wait
(SPICT)
92CF26A-489
; Load “A” the tranmit data
; Disable the interrupt
; Start transmission be setting the TXE bit to 1
; Disable the transmission by clearing the TXE bit to 0
; Enable the interrupt
; Load the tranmit data
; Disable the interrupt
; Start transmission by setting the TXE bit to 1
; Wait for the completion of the transmission
; Disable the transmission by clearing the TXE bit to 0
; Enable the interrupt
TMP92CF26A
2007-11-21