TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 437

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(c-4) Stage management
•
•
Each stage in control transfer type has to process combination software. UDC detects
the following contents from 8-byte data in SETUP stage. The stage is managed by
determining control transfer type.
transfer type, or control write transfer type (No data stage).
of internal UDC, NAK handshake is returned and BUSY is informed to USB host. In
all control transfer types, if SETUP token is received from host current transaction is
stopped, and it switches to SETUP stage in the UDC. The CPU receives new
INT_SETUP even if it is processing previous control transfer.
The UDC manages each stage of control transfer by hardware.
Each stage is changed by receiving token from USB host, or CPU accesses register.
Based on these it is determines to be either control read transfer type control write
Various conditions for changing stage in control transfer are given below.
If receiving token for next stage from host before switching to next stage from state
Whether there is data stage or not
Data stage direction
92CF26A-436
TMP92CF26A
2007-11-21