SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 112

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5.2
5.2.1
5-4
TCM interface signals
Data interface signals
The TCM interface is designed to be compatible the timings of standard ASIC SRAM
components, allowing connection to single cycle SRAM with minimal interfacing logic
required. For standard SRAM the chip-select, address, and write data/control signals are
setup in one cycle, and the read or write operation takes place in the next cycle.
The signals in the DTCM interface can be grouped by function into four categories.
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Control signals
The control signals for the data interface are:
DRCS
DRCS is used to indicate that an access will commence in the following cycle. For
simple zero wait state TCM systems the DRCS signals corresponds directly to a
memory chip select signal. For more complex systems DRCS corresponds to a memory
request signal.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Control signals
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Address and attribute signals
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Data signals
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DMA signals
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DRCS
DRWAIT
DRIDLE
DRSEQ
DRADDR[17:0]
DRWBL[3:0]
DRnRW
DRRD[31:0]
DRWD[31:0]
DRDMAEN
DRDMACS
DRDMAADDR[17:0].
ARM DDI0198D