SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 154

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Noncachable Instruction Fetches
7.1
7.1.1
7.1.2
7-2
About noncachable instruction fetches
Uses of noncachable code
Self modifying code
The ARM926EJ-S processor performs speculative noncachable instruction fetches to
increase performance. Speculative instruction fetching is enabled at reset. This can be
disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register
c15 on page 2-36). If prefetching is disabled only instruction fetches issued directly by
the ARM9EJ-S core result in instruction fetches on the AHB interface.
The following subsection is divided into:
•
•
•
Although noncachable code performance has been improved compared with other
ARM9 family cached cores, it is still recommended that the ICache is used in
preference, where practical.
Noncachable code has previously been used for boot loaders of operating systems and
for preventing cache pollution. It is worth noting that the ICache can be enabled without
the MMU being enabled (see Chapter 4 Caches and Write Buffer), and that cache
pollution can be controlled using the cache lockdown register (see Cache Lockdown and
TCM Region Registers c9 on page 2-26).
A four-word buffer is used to hold speculatively fetched instructions. Only sequential
instructions are fetched speculatively, and in the event of the ARM9EJ-S core issuing a
nonsequential instruction fetch, the contents of the buffer are discarded (flushed). In
situations where the contents of the prefetch buffer might become invalid during a
sequence of sequential instruction fetches by the ARM9EJ-S core (for example, turning
the MMU on or off, or turning on the ICache), the prefetch buffer is also flushed. This
avoids the requirement for an explicit Instruction Memory Barrier (IMB) operation to
be performed, except when self-modifying code is used. Because the prefetch buffer is
flushed when the ARM9EJ-S core issues a nonsequential instruction fetch, a branch
instruction (or equivalent) can be used to implement the required IMB behavior. This is
illustrated by the following code sequence:
Copyright © 2001-2003 ARM Limited. All rights reserved.
Uses of noncachable code
Self modifying code
AHB behavior on page 7-3.
ARM DDI0198D