SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 118

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5.3.2
5-10
DMA access to zero wait state TCM
DRADDR
DRWBL
DRSEQ
DRWD
DnRW
DRCS
DRRD
CLK
In cycle T1, a nonsequential read request is made to address A.
In cycle T2, a nonsequential word write request is made to address B and data is
returned for the access to A.
In cycle T3, no request is made.
In cycle T4, a nonsequential read request is made to address C.
In cycle T5, a sequential read request is made to address C+1 and data is returned for
the access to C.
In cycle T6, a nonsequential byte write request is made to address D.
For DMA accesses to zero wait state memories, the TCM DMA interface can be used
which enables an alternative source of address and chip-select to be passed through to
the TCM memories without impacting timing. Figure 5-4 on page 5-11 shows the
relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and
DRCS.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T1
A
0000
T2
B
D(B)
1111
D(A)
T3
Figure 5-3 Data side zero wait state accesses
T4
C
0000
T5
C+1
D(C)
T6
D
D(D)
D(C+1)
0001
ARM DDI0198D
T7