SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 139

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.8
ARM DDI0198D
Using synchronous SRAM as TCM memory
If you use SRAM to implement TCM memory, then your library RAM must meet the
following requirements:
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Ideally each TCM can be constructed from single RAM blocks. However, this is not
always possible for the following reasons:
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Ideally, your RAM block can connect directly to the ARM926EJ-S TCM interface.
However, this is not always possible, and additional logic is required in the following
cases:
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DRADDR is always a word address. DRWBL is used as a byte lane strobe to select the
appropriate byte of the addressed word on writes. Reads are always word-wide.
Copyright © 2001-2003 ARM Limited. All rights reserved.
It must be synchronous. All timings must be relative to the rising clock edge.
It must have a chip select (RAM enable).
The RAM outputs must always be valid. They must not be tristated.
Byte write control is required.
RAM setup times must be less than 10-15% and access times must be less than
40-50% of the target cycle time. Violation of these requirements results in a
slower design. Setup and access times can be balanced by skewing the clock to
the RAM.
If your RAM does not have byte write control, you must construct the word-wide
RAM out of four byte-wide RAMs. See Producing byte writable memory using
word writable RAM on page 5-20.
If your compiler cannot produce a single RAM block that is the required size, or
if a single RAM block does not meet the timing requirements. In these cases, you
must produce the RAM out of two or more blocks of smaller RAM. See Multiple
banks of RAM example on page 5-21.
All TCM signals are driven as active HIGH. If your RAM requires active LOW
signals, you must add inverters to create the active LOW signals.
If power control logic is required.
If a RAM is non single-cycle, or hardware DMA arbitration is required, logic is
required to drive the appropriate wait signal.
Note
Tightly-Coupled Memory Interface
5-31