SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 122

no-image

SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Tightly-Coupled Memory Interface
5-14
In the WAIT state IRWAIT is asserted. In the COMPLETE state IRWAIT is
deasserted.
Certain types of memories can have different access penalties depending on whether an
access is sequential or nonsequential. The IRSEQ/DRSEQ signals indicate if an access
is sequential in the request cycle for an access, and are held HIGH during waited cycles.
This behaviour enables a loopback arrangement, where the SEQ output can be fed
directly back into the WAIT input through an inverter to produce a single cycle wait
state for nonsequential accesses as shown in Figure 5-8.
The cycle timing of the circuit shown in Figure 5-8 is shown in Figure 5-9 on page 5-15.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Figure 5-8 Loopback of SEQ to produce a single cycle wait state
Figure 5-7 State machine for generating a single wait state
IRADDR[17:0]
IRRD[31:0]
IRWAIT
IRSEQ
IRCS
COMPLETE
IRCS = 0
WAIT
ARM DDI0198D
IRCS = 1
TCM

Related parts for SAM9G45