SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 182

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Support
11.1
11.1.1
11.1.2
11-2
About debug support
Debug clocks
Scan chain 15
Debug support is implemented by using the ARM9EJ-S core embedded within the
ARM926EJ-S processor. Full details of the debug support provided by the ARM9EJ-S
core are described in the ARM9EJ-S Technical Reference Manual.
Debug support for the ARM926EJ-S memory system is implemented by extending the
debug facilities providing access to CP15 using an ARM9EJ-S external scan chain (scan
chain 15). This scan chain is external to the ARM9EJ-S core but internal to the
ARM926EJ-S processor.
The system and test clocks must be synchronized externally to the ARM926EJ-S
macrocell. To synchronize off-chip debug clocking with the ARM926EJ-S macrocell
requires a three-state synchronizer. This is described in the debug chapter of the
ARM9EJ-S Technical Reference Manual.
Scan chain 15 enables access to the CP15 registers. Scan chain 15 is 48 bits long.
Table 11-1 shows the bit assignments for scan chain 15.
With scan chain 15 selected, TDI is connected to bit 47 and TDO is connected to bit 0.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Bits
[47]
[46:33]
[32]
[31:0]
Table 11-1 Scan chain 15 format
Write, not read (W/R)
Register address
Initiate access/access complete
When written:
1 = initiate new access
0 = NOP
When read:
1 = access complete
0 = access incomplete
Data value
Function
ARM DDI0198D