SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 183

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
To perform an access using scan chain 15, you must:
1.
2.
3.
4.
5.
If Multi-ICE is used, then this has the restriction that a maximum of 40 bits of any scan
chain can be written at a time. Because scan chain 15 is 48 bits long, CP15 register
writes require two operations to write all the required bits, and initiate the access. This
can be done by first writing bits [31:0] with the required data value, and bit 32 to 0. This
has the effect of presetting the data value field for the next operation. The second
operation sets bits [47:33] to the required values, and bit 32 to 1 to initiate the access.
This relies on the specific behavior of scan chain 15, which enables data to be
recirculated if a value is scanned in with bit 32 set to 0, and there is no pending access.
In this case the transition through UPDATE-DR does not modify the contents of the
scan chain, and the value written in can safely be read back out in a subsequent
CAPTURE-DR, SHIFT-DR sequence.
The mapping of scan chain 15 to CP15 registers is done in the same way as a CP15
MRC/MCR operation. Bits [46:33] of the scan chain are mapped onto Opcode_1,
Opcode_2, CRn, and CRm.
Copyright © 2001-2003 ARM Limited. All rights reserved.
During the SHIFT-DR state of the TAP state machine, shift in the read/write bit,
register address, and register data value for writing, with bit 32 set to 1. For read
operations the data value field does not have to be written.
Move through UPDATE-DR. The operation specified by the register address and
write not read bits does not start.
Return to SHIFT-DR and perform a shift operation so that bits 32, and [31:0] are
read, and a NOP instruction (bit 32 = 0) is shifted in.
Move through UPDATE-DR. No operation is performed because bit 32 is 0.
Check the access complete value that is shifted out. If it is 1, the operation has
completed and bits [31:0] contain valid data for reads. If it is 0, the access has not
completed and you must go back to step 3.
Note
Debug Support
11-3