SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 98

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Caches and Write Buffer
4.1
4-2
About the caches and write buffer
The ARM926EJ-S processor includes:
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The size of the caches can be from 4KB to 128KB, in power of two increments.
The caches have the following features:
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Copyright © 2001-2003 ARM Limited. All rights reserved.
an Instruction Cache (ICache)
a Data Cache (DCache)
a write buffer.
The caches are virtual index, virtual tag, addressed using the Modified Virtual
Address (MVA). This enables the avoidance of cache cleaning and/or invalidating
on context switch.
The caches are four-way set associative, with a cache line length of eight words
per line (32 bytes per line), and with two dirty bits in the DCache.
The DCache supports write-through and write-back (or copyback) cache
operations, selected by memory region using the C and B bits in the MMU
translation tables.
Allocate on read-miss is supported. The caches perform critical-word first cache
refilling.
Pseudo-random or round-robin replacement, selectable by the RR bit in CP15 c1.
Cache lockdown registers enable control over which cache ways are used for
allocation on a linefill, providing a mechanism for both lockdown and controlling
cache pollution.
The DCache stores the Physical Address (PA) tag corresponding to each DCache
entry in the tag RAM for use during cache line write-backs, in addition to the
Virtual Address tag stored in the tag RAM. This means that the MMU is not
involved in DCache write-back operations, removing the possibility of TLB
misses related to the write-back address.
The PLD data preload instruction does not cause data cache linefills. It is treated
as a NOP instruction.
Cache maintenance operations to provide efficient invalidation of:
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They also provide operations for efficient cleaning and invalidation of:
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the entire DCache or ICache
regions of the DCache or ICache
regions of virtual memory.
the entire DCache
regions of the DCache
regions of virtual memory.
ARM DDI0198D