SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 204

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Descriptions
A-16
Signal
IRDMAADR[17:0]
IRDMAEN
IRDMACS
IRIDLE
IRnRW
IRRD[31:0]
IRSEQ
IRSIZE[3:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Input
Input
Input
Output
Output
Input
Output
Input
Function
DMA access cycle.
If asserted, IRADDR is directly sourced from
IRDMAADDR, and IRCS is the result of logically
ORing IRDMACS with the chip select value for the
current TCM access.
Enables direct memory access to the ITCM memory
using the IRDMAADDR and IRDMACS inputs.
Direct memory access chip-select for ITCM.
Instruction TCM interface idle:
0 = TCM access
1 = no access will take place in the current cycle or
TCM disabled.
Not valid for DMA accesses.
Instruction TCM read not write:
0 = read
1 = write.
Indicates if the access is a read or write. Valid during
request cycles.
Instruction TCM read data.
Valid during non-waited data cycles.
Request sequential.
Valid during request cycles, asserted during wait
cycles.
Indicates that the address in the current cycle is
sequential to the address used during the previous
request cycle.
IRSEQ is not valid following ITCM DMA accesses.
Instruction TCM size.
Static configuration input that specifies the physical
size of TCM memories attached.
0000 = absent
0011 = 4KB
0100 = 8KB
…
1010 = 512KB
1011 = 1MB
Values 0001, 0010, and 1100 to 1111 are reserved.
Table A-7 TCM interface signals (continued)
ARM DDI0198D