SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 53

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
ARMv4/ARMv5 operation
Invalidate TLB
Invalidate TLB single entry (MVA)
Invalidate instruction TLB
Invalidate instruction TLB single entry (MVA)
Invalidate data TLB
Invalidate data TLB single entry (MVA)
The fully-associative part (also referred to as the lockdown part of the TLB) is used to
store entries to be locked down. Entries held in the lockdown part of the TLB are
preserved during an invalidate TLB operation. Entries can be removed from the
lockdown TLB using an invalidate TLB single entry operation.
Six TLB operations are defined, and the function to be performed is selected by the
Opcode_2 and CRm fields in the MCR instruction used to write CP15 c8. Writing other
Opcode_2 or CRm values is Unpredictable. Reading from this register is Unpredictable.
You can use the instructions shown in Table 2-19 to perform TLB operations.
Those instructions that are intended to be used with dual TLB implementations (such as
the ARM920T core or the ARM1020T core) apply to any entry, regardless of the type
of access that caused the entry to be loaded into the TLB (see the ARM Architecture
Reference Manual).
The invalidate TLB operations invalidate all the unpreserved entries in the TLB. The
invalidate TLB single entry operations invalidate any TLB entry corresponding to the
Modified Virtual Address given in Rd, regardless of its preserved state. See TLB
Lockdown Register c10 on page 2-32 for a description of how to preserve entries in the
TLB.
Figure 2-11 on page 2-26 shows the Modified Virtual Address format used for
invalidate TLB single entry operations.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM926EJ-S operation
Invalidate set-associative TLB
Invalidate single entry
Invalidate set-associative TLB
Invalidate single entry
Invalidate set-associative TLB
Invalidate single entry
Table 2-19 Register c8 TLB operations
Data
SBZ
MVA
SBZ
MVA
SBZ
MVA
Instruction
Programmer’s Model
2-25