SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 43

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
Cache
ICache disabled
ICache enabled
ICache enabled
DCache disabled
DCache enabled
DCache enabled
MMU
Enabled or
disabled
Disabled
Enabled
Enabled or
disabled
Disabled
Enabled
•
Assuming that TCM regions are disabled, the caches behave as shown in Table 2-12.
If either the DCache or the ICache is disabled, then the contents of that cache are not
accessed. If the cache is subsequently re-enabled, the contents will not have changed.
To guarantee that memory coherency is maintained, the DCache must be cleaned of
dirty data before it is disabled.
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the RR bit.
Behavior
All instruction fetches are from external memory (AHB).
All instruction fetches are cachable, with no protection checks. All addresses are flat
mapped. That is VA = MVA = PA.
Instruction fetches are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
All data accesses are to external memory (AHB).
All data accesses are noncachable nonbufferable. All addresses are flat mapped. That
is VA = MVA = PA.
All data accesses are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
Table 2-12 Effects of Control Register on caches
Programmer’s Model
2-15