SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 38

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2-10
Assoc
M bit
Len
The size of the cache is determined by the Size field and the M bit. The M bit is 0 for
the DCache and ICache. The Size field is bits [21:18] for the DCache and bits [9:6] for
the ICache. The minimum size of each cache is 4KB, and the maximum size is 128KB.
Table 2-7 shows the cache size encoding.
The associativity of the cache is determined by the Assoc field and the M bit. The M bit
is 0 for the DCache and ICache. The Assoc field is bits [17:15] for the DCache and bits
[5:3] for the ICache. Table 2-8 shows the cache associativity encoding.
Copyright © 2001-2003 ARM Limited. All rights reserved.
The Assoc field determines the cache associativity in conjunction with
the M bit.
The multiplier bit determines the cache size and cache associativity
values in conjunction with the Size and Assoc fields. If the cache is
present, M must be set to 0. If the cache is absent, M must be set to 1. For
the ARM926EJ-S processor, M is always set to 0.
The Len field determines the line length of the cache.
Table 2-8 Cache associativity encoding (M=0)
Table 2-7 Cache size encoding (M=0)
Assoc field
b010
Other values
Size field
b0011
b0100
b0101
b0110
b0111
b1000
Associativity
4-way
Reserved
ARM DDI0198D
Cache size
4KB
8KB
16KB
32KB
64KB
128KB