SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 211

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.1.3
B.1.4
ARM DDI0198D
Trace Control Register
MMU test operations
Instruction
You can access the Trace Control Register by using the following instructions:
You can use the Trace Control Register to determine under what conditions the
ARM9EJ-S core is stalled when the FIFOFULL signal is asserted.
Usually, non-invasive real-time trace requires the presence of an nFIQ or nIRQ
interrupt to prevent the ARM9EJ-S core being stalled by FIFOFULL being asserted.
The Trace Control Register enables you to modify this behavior, so that the presence of
an interrupt does not prevent the ARM9EJ-S core being stalled if FIFOFULL is
asserted.
Table B-2 shows the bit assignments for the Trace Control Register. Bits [2:1] of this
register are reset to 0.
The MMU test operations support accessing TLB structures in the MMU and are used
in conjunction with the Debug and Test Address Register.
You can access the MMU test operations using the instructions in Table B-3.
[31:3]
[2]
[1]
[0]
Bits
Copyright © 2001-2003 ARM Limited. All rights reserved.
Content
Reserved (Should Be Zero)
1 = FIQ interrupt does not prevent FIFOFULL from stalling the ARM9EJ-S core
0 = FIQ interrupt prevents FIFOFULL from stalling the ARM9EJ-S core
1 = IRQ interrupt does not prevent FIFOFULL from stalling the ARM9EJ-S core
0 = IRQ interrupt prevents FIFOFULL from stalling the ARM9EJ-S core
Reserved (Should Be Zero)
Operation
Read tag in main TLB entry
Write tag in main TLB entry
Table B-2 Trace Control Register bit assignments
Table B-3 MMU test operation instructions
CP15 Test and Debug Registers
B-5