SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 162

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.3
8-6
MCR/MRC
Coprocessor pipeline
CPLATECANCEL
CPINSTR[31:0]
CPDOUT[31:0]
CPDIN[31:0]
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
MCR
MRC
CLK
These cycles look very similar to STC/LDC. An example with a busy-wait state is
shown in Figure 8-4.
First, nCPMREQ is driven LOW to indicate that the instruction on CPINSTR is
entering the Decode stage of the pipeline. This coprocessor decodes the new instruction
and drives CHSDE[1:0] as required.
In the next cycle, nCPMREQ is driven LOW to indicate that the instruction has now
been issued to the Execute stage. If the condition codes pass and the instruction is to be
executed, the CPPASS signal is driven HIGH and the CHSDE[1:0] handshake bus is
examined (it is ignored in all other cases).
For any successive execute cycles the CHSEX[1:0] handshake bus is examined. When
the LAST condition is observed, the instruction is committed. In the case of an MCR,
the CPDOUT[31:0] bus is driven with the register data during the coprocessor Write
stage. In the case of an MRC, CPDIN[31:0] is sampled at the end of the ARM9EJ-S
memory stage and written to the destination register during the next cycle.
MCR/MRC
Copyright © 2001-2003 ARM Limited. All rights reserved.
Fetch
Decode
WAIT
Execute
(WAIT)
LAST
Execute
(LAST)
Ignored
Coproc data
Figure 8-4 MCR/MRC cycle timing
Memory
Coproc data
Write
ARM DDI0198D