SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 67

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.1.1
3.1.2
ARM DDI0198D
Access permissions and domains
Translated entries
For large and small pages, access permissions are defined for each subpage (1KB for
small pages, 16KB for large pages). Sections and tiny pages have a single set of access
permissions.
All regions of memory have an associated domain. A domain is the primary access
control mechanism for a region of memory. It defines the conditions necessary for an
access to proceed. The domain determines if:
•
•
•
In the latter two cases, the access permission attributes are ignored.
There are 16 domains. These are configured using the domain access control register
(see Domain Access Control Register c3 on page 2-17).
The main TLB caches 64 translated entries. If, during a memory access, the main TLB
contains a translated entry for the MVA, the MMU reads the protection data to detrmine
if the access is permitted:
•
•
•
If the TLB misses (it does not contain an entry for the MVA) the translation table walk
hardware is invoked to retrieve the translation information from a translation table in
physical memory. When retrieved, the translation information is written into the TLB,
possibly overwriting an existing value.
To enable use of TLB locking features, the location to be written can be specified using
CP15 c10 TLB Lockdown Register.
At reset the MMU is turned off, no address mapping occurs, and all regions are marked
as noncachable and nonbufferable.
Copyright © 2001-2003 ARM Limited. All rights reserved.
access permissions are used to qualify the access
the access is unconditionally allowed to proceed
the access is unconditionally aborted.
if access is permitted and an off-chip access is required, the MMU outputs the
appropriate physical address corresponding to the MVA
if access is permitted and an off-chip access is not required, the cache or TCM
services the access
if access is not permitted, the MMU signals the CPU core to abort.
Memory Management Unit
3-3