SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 8

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

List of Tables
viii
Table 2-23
Table 2-24
Table 2-25
Table 2-26
Table 2-27
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 4-7
Table 5-1
Table 6-1
Table 6-2
Table 8-1
Table 8-2
Table 11-1
Table 11-2
Table A-1
Table A-2
Table A-3
Table A-4
Table A-5
Table A-6
Table A-7
Table B-1
Table B-2
Table B-3
Table B-4
Table B-5
Table B-6
Table B-7
Table B-8
Table B-9
TCM Region Register c9 ........................................................................................ 2-30
TCM Size field encoding ......................................................................................... 2-30
Programming the TLB Lockdown Register ............................................................. 2-32
FCSE PID Register operations ............................................................................... 2-34
Context ID register operations ................................................................................ 2-35
MMU program-accessible CP15 registers ................................................................ 3-4
First-level descriptor bits ........................................................................................... 3-9
Interpreting first-level descriptor bits [1:0] ............................................................... 3-10
Section descriptor bits ............................................................................................ 3-11
Coarse page table descriptor bits ........................................................................... 3-12
Fine page table descriptor bits ................................................................................ 3-13
Second-level descriptor bits .................................................................................... 3-15
Interpreting page table entry bits [1:0] .................................................................... 3-16
Priority encoding of fault status ............................................................................... 3-22
FAR values for multi-word transfers ....................................................................... 3-23
Domain access control register, access control bits ............................................... 3-24
Interpreting access permission (AP) bits ................................................................ 3-24
CP15 c1 I and M bit settings for the ICache ............................................................. 4-5
Page table C bit settings for the ICache ................................................................... 4-5
CP15 c1 C and M bit settings for the DCache .......................................................... 4-6
Page table C and B bit settings for the DCache ....................................................... 4-6
Instruction access priorities to the TCM and cache .................................................. 4-8
Data access priorities to the TCM and cache ........................................................... 4-8
Values of S and NSETS ......................................................................................... 4-10
Relationship between DMDMAEN, DRDMACS, and DRIDLE ................................. 5-6
Supported HBURST encodings ................................................................................ 6-4
IHPROT[3:0] and DHPROT[3:0] attributes ............................................................... 6-5
Handshake signal encoding ...................................................................................... 8-5
CPBURST encoding ............................................................................................... 8-11
Scan chain 15 format .............................................................................................. 11-2
Scan chain 15 mapping to CP15 registers ............................................................. 11-4
AHB related signals .................................................................................................. A-3
Coprocessor interface signals .................................................................................. A-5
Debug signals ........................................................................................................... A-7
JTAG signals ............................................................................................................ A-9
Miscellaneous signals ............................................................................................. A-10
ETM interface signals ............................................................................................. A-12
TCM interface signals ............................................................................................. A-14
Debug Override Register .......................................................................................... B-3
Trace Control Register bit assignments .................................................................... B-5
MMU test operation instructions ............................................................................... B-5
Encoding of the main TLB entry-select bit fields ....................................................... B-6
Encoding of the TLB MVA tag bit fields .................................................................... B-7
Encoding of the TLB entry PA and AP bit fields ....................................................... B-8
Main TLB mapping to MMUxWD .............................................................................. B-9
Encoding of the lockdown TLB entry-select bit fields ............................................. B-11
Cache Debug Control Register bit assignments ..................................................... B-12
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