SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 131

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
ARM926EJ-S
Optimizing for speed
Figure 5-15 on page 5-24 shows how to produce a large memory from two smaller
RAM blocks if you are optimizing for speed. Separate write enable control is required
for each RAM block:
WE_bank0 = ~DRADDR[14] & DRnRW
WE_bank1 = DRADDR[14] & DRnRW
No logic is added to the critical DRCS path, but both RAMs are enabled whenever
DRCS is asserted, resulting in higher power consumption.
DRADDR[17:0]
DRWD[31:0]
DRWBL[3:0]
DRSIZE[3:0]
DRRD[31:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRWAIT
DRnRW
DRIDLE
DRSEQ
DRCS
b1000
DRADDR[14]
CLK
DIN[31:0]
CLK
WE
CS DOUT[31:0]
RAM 64KB
A[13:0]
Bank 1
DRADDR[13:0]
BW[3:0]
Figure 5-14 Optimizing for power
Tightly-Coupled Memory Interface
DIN[31:0]
CLK
WE
CS DOUT[31:0]
RAM 64KB
A[13:0]
Bank 0
DRADDR[13:0]
BW[3:0]
5-23