SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 68

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Management Unit
3.1.3
3-4
MMU program accessible registers
Register
Control register
c1
Translation table
base register c2
Domain access
control register
c3
Fault status
registers, IFSR
and DFSR, c5
Fault address
register c6
TLB operations
register c8
TLB lockdown
register c10
Table 3-1 shows the CP15 registers that are used in conjunction with page table
descriptors stored in memory to determine the operation of the MMU.
All the CP15 MMU registers, except c8, contain state that can be read using MRC
instructions, and written using MCR instructions. Registers c5 and c6 are also written
by the MMU during an abort. Writing to c8 causes the MMU to perform a TLB
operation, to manipulate TLB entries. This register is write-only.
The CP15 registers are described in Chapter 2 Programmer’s Model.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Bits
M, A, S, R
[31:14]
[31:0]
[7:0]
[31:0]
[31:0]
[28:26] and
[0]
Register description
Contains bits to enable the MMU (M bit), enable data address alignment
checks (A bit), and to control the access protection scheme (S bit and R
bit).
Holds the physical address of the base of the translation table
maintained in main memory. This base address must be on a 16KB
boundary.
Comprises 16 two-bit fields. Each field defines the access control
attributes for one of 16 domains (D15 to D0).
Indicates the cause of a Data or Prefetch Abort, and the domain number
of the aborted access, when an abort occurs. Bits [7:4] specify which of
the 16 domains (D15 to D0) was being accessed when a fault occurred.
Bits [3:0] indicate the type of access being attempted. The value of all
other bits is Unpredictable. The encoding of these bits is shown in
Table 3-9 on page 3-22.
Holds the MVA associated with the access that caused the Data Abort.
See Table 3-9 on page 3-22 for details of the address stored for each
type of fault. The ARM9EJ-S register R14_abt holds the VA associated
with a Prefetch Abort.
This register is used to perform TLB maintenance operations. These are
either invalidating all the (unpreserved) entries in the TLB, or
invalidating a specific entry.
Enables specific page table entries to be locked into the TLB. Locking
entries in the TLB guarantees that accesses to the locked page or section
can proceed without incurring the time penalty of a TLB miss. This
enables the execution latency for time-critical pieces of code such as
interrupt handlers to be minimized.
Table 3-1 MMU program-accessible CP15 registers
ARM DDI0198D