SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 186

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Power Management
12.1
12.1.1
12-2
About power management
Dynamic power management (wait for interrupt mode)
The power management facilities provided by the ARM926EJ-S processor are:
•
•
The ARM926EJ-S processor can be put into a low-power state by the wait for interrupt
instruction:
This instruction switches the ARM926EJ-S processor into a low-power state until either
an interrupt (IRQ or FIQ) or a debug request occurs. The debug request can either be an
external debug request EDBGRQ or a debug request made by the debugger by writing
to the DBGRQ bit of the ARM9EJ-S debug control register using scan chain 2.
In wait for interrupt mode, all internal ARM926EJ-S clocks can be stopped. The switch
into the low-power state is delayed until all write buffers have been drained, and the
ARM926EJ-S memory system is in a quiescent state.
The switch into low-power state is indicated by the assertion of the STANDBYWFI
signal. If STANDBYWFI is asserted then it is guaranteed that all of ARM926EJ-S
external interfaces (AHB, TCM, and external coprocessor) are in an idle state. The
STANDBYWFI signal is intended to be used to shut down clocks to other parts of the
system, such as external coprocessors, that do not have to be clocked if the
ARM926EJ-S processor is idle.
The STANDBYWFI signal is deasserted in the second cycle following an interrupt or
a debug request. It is guaranteed that no form of access on any external interface is
started until the cycle after STANDBYWFI is deasserted. Figure 12-1 shows the
deassertion of the STANDBYWFI signal after an IRQ interrupt.
STANDBYWFI
Copyright © 2001-2003 ARM Limited. All rights reserved.
Dynamic power management (wait for interrupt mode)
Static power management (leakage control) on page 12-3.
nIRQ
CLK
Figure 12-1 Deassertion of STANDBYWFI after an IRQ interrupt
ARM DDI0198D