SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 160

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.2
8-4
CPLATECANCEL
CPDOUT[31:0]
CPINSTR[31:0]
CPDIN[31:0]
CHSDE[1:0]
CHSEX[1:0]
Coprocessor
nCPMREQ
CPPASS
pipeline
LDC/STC
LDC
STC
CLK
Fetch
LDC
The cycle timing for this operation is shown in Figure 8-3.
In Figure 8-3 four words of data are transferred. The number of words transferred is
determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.
As with all other instructions, the ARM9EJ-S core performs the main decode off the
rising edge of the clock during the Decode stage. From this, the core commits to
executing the instruction and so performs an instruction fetch. The coprocessor
instruction pipeline keeps in step with the ARM9EJ-S core by monitoring nCPMREQ.
nCPMREQ is an active LOW signal that indicates if the ARM9EJ-S pipeline has
advanced. CPINSTR is updated with the fetched instruction in the next cycle. This
means that the instruction currently on CPINSTR must enter the Decode stage of the
coprocessor pipeline, and that the instruction in the Decode stage of the coprocessor
pipeline must enter its Execute stage.
During the Execute stage, the condition codes are combined with the flags to determine
if the instruction executes or not. The output CPPASS is asserted HIGH if the
instruction in the Execute stage of the coprocessor pipeline:
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
Decode
is a coprocessor instruction
has passed its condition codes.
GO
Execute
(GO)
GO
Execute
(GO)
GO
Execute
(GO)
LAST
Execute
(LAST)
Figure 8-3 LDC/STC cycle timing
Ignored
Memory
ARM DDI0198D
Write