SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 57

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
7.
8.
Cache unlock procedure
To unlock the locked down portion of the cache, write to register c9 setting L == 0 for
the appropriate bit. For example, the following sequence sets the L bit to 0 for way 0 of
the ICache, unlocking way 0:
TCM Region Register c9
The ARM926EJ-S processor supports physically-indexed, physically-tagged TCM.
The TCM Region Register supports one region of instruction TCM and one region of
data TCM. The minimum size of TCM region that can be supported is 4KB. The TCM
Status Register indicates if TCM memories are attached (see TCM Status Register c0 on
page 2-12). The size of each TCM region is defined by the DRSIZE and IRSIZE input
pins.
The data TCM is always disabled at reset. The instruction TCM is enabled at reset if the
INITRAM pin is HIGH. This enables booting from the instruction TCM and sets the
ITCM enable bit in the ITCM region register. You can use the TCM Region Register
instructions listed in Table 2-22.
Copyright © 2001-2003 ARM Limited. All rights reserved.
For each of the cache lines to be locked down in cache way i:
•
•
Write to register c9, CRm == 0 setting L == 1 for bit i and restoring all the other
bits to the values they had before the lockdown routine was started.
Function
Read data TCM Region Register
Write data TCM Region Register
Read instruction TCM Region Register
Write instruction TCM Region Register
If a DCache is being locked down, use an LDR instruction to load a word
from the memory cache line to ensure that the memory cache line is loaded
into the cache.
If an ICache is being locked down, use the register c7 MCR prefetch ICache
line (CRm == c13, Opcode2 == 1) to fetch the memory cache line into the
cache.
Table 2-22 TCM Region Register instructions
Data
Base address
Base address
Base address
Base address
Instruction
Programmer’s Model
2-29