SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 59

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
If either the data or instruction TCM is disabled, then the contents of the respective
TCM are not accessed. If the TCM is subsequently re-enabled, the contents will not
have been changed by the ARM926EJ-S processor.
For a Harvard arrangement, the instruction-side TCM must be accessible for both reads
and writes during normal operation, and for loading code, or for debug activity. This
enables accesses to literal pools, undefined instruction emulation, and parameter
passing for SWI operations. You must insert an Instruction Memory Barrier (IMB)
between a write to the instruction TCM and the instructions being read from the
instruction TCM. See Chapter 9 Instruction Memory Barrier for more details.
Instruction fetches from the data TCM are not possible. An attempt to fetch an
instruction from an address in the data TCM space does not result in an access to the
data TCM, and the instruction is fetched from main memory. These accesses can result
in external aborts, because the address range might not be supported in main memory.
The instruction TCM must not be programmed to the same base address as the data
TCM. If the two TCMs are of different sizes, the regions in physical memory must not
overlap. If they do overlap, it is Unpredictable which memory is accessed.
The base address value setting must be aligned to the TCM size.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Note
Table 2-24 TCM Size field encoding (continued)
Memory
size
64KB
128KB
256KB
512KB
1MB
Reserved
Programmer’s Model
Value
b0111
b1000
b1001
b1010
b1011
b1100, b1101,
b1110, b1111
2-31