SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 19

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
ARM DDI0198D
Signal naming
The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
signals:
Prefix H
Prefix n
Prefix DH
Prefix IH
Prefix DR
Prefix IR
Prefix ETM Denotes ETM interface signals.
Prefix DBG Denotes debug/JTAG signals.
Prefix CP
Copyright © 2001-2003 ARM Limited. All rights reserved.
Denotes Advanced High-performance Bus (AHB) signals.
Denotes active-LOW signals except in the case of AHB or Advanced
Peripheral Bus APB reset signals. These are named HRESETn and
PRESETn respectively.
Denotes data side AHB signals.
Denotes instruction side AHB signals.
Denotes data side TCM interface signals.
Denotes instruction side TCM interface signals.
Denotes coprocessor interface signals.
High impedance to stable bus
Key to timing diagram conventions
Bus to high impedance
HIGH/LOW to HIGH
HIGH to LOW
Bus change
Bus stable
Transient
Clock
Preface
xix

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